In recent years, with the advance of digital technologies, electronic devices such as portable information devices and information home appliances have been increasingly sophisticated. There are therefore greater demands for a nonvolatile memory device with higher capacity, less writing power, higher writing/reading speed, and longer service life.
In order to meet the demands, refinement of a flash memory with existing floating gates has been progressed. On the other hand, as a substitute element for a flash memory, a nonvolatile memory device including memory elements each having a so-called variable resistance memory element has been researched and developed. The variable resistance memory element has a resistance value that changes according to electrical signal. The changed resistance value is kept even after turning the electrical signal off (in other words, kept in a nonvolatile manner). The variable resistance memory element is therefore capable of holding data according to the change of the resistance value.
Typical examples of the variable resistance memory element are a Magnetic Random Access Memory (MRAM), a Phase Change Random Access Memory (PRAM), a Resistec Random Access Memory (ReRAM), and the like.
One example of a structure of a nonvolatile memory device having such a variable resistance memory element is known as a crosspoint structure. In the crosspoint structure, each of memory cells is provided, between a bit line and a word line, at a corresponding crosspoint between the bit line and the word line which are arranged perpendicular to each other. Each of the memory cells includes a memory element that is a single variable resistance memory element. Or, each memory cell includes a variable resistance memory element and a switching element which are connected in series. The switching element, such as a diode, has nonlinear characteristics. An electrode of the memory element is connected to a word line, and the other electrode is connected to a bit line. The crosspoint structure has characteristics of being more suitable for large-scale integration than a so-called 1T1R (1 transistor and 1 resistance) structure where a variable resistance memory element is connected to a bit line via an access transistor.
In the crosspoint structure, a plurality of memory cells are arranged in an array to form a crosspoint cell array. In the crosspoint structure, in order to detect (read) a resistance value of a memory element included in a target memory cell, a reading voltage is applied to a corresponding bit line and a corresponding word line. When the reading voltage is applied, a current flows in the target memory cell to be detected (target to be read), but a current also flows via the other memory cells (memory cells other than the target memory cell) connected in parallel to the target memory cell along upper and lower lines, namely, a bit line and a word line. In the description, the “current (that) also flows via the other memory cells” is referred to as a sneak current.
The sneak current changes according to a state of pieces of data stored in a crosspoint cell array (namely, resistance values of memory elements included in all of memory cells in the crosspoint cell array to which a target memory cell to be detected belongs, and distribution of the resistance values). Therefore, a current detected in reading includes a sneak current having a value that constantly varies. Such a sneak current prevents accurate detection of a resistance value of a memory element included in a target memory cell to be read. Patent Literature 1 (PLT1) discloses a semiconductor memory device having a structure for preventing a sneak current from decreasing a detection sensitivity of a resistance value of a memory element included in a memory cell.
It has been generally known that an operation called forming is necessary to cause a variable resistance memory element to be in the state where a resistance of the variable resistance memory element is reversibly changeable. A technique relating to the forming is disclosed in Patent Literature 2 (PLT 2).
Furthermore, as a means for causing a crosspoint semiconductor memory device to perform correct forming, Patent Literature 3 discloses a structure including a detection circuit that detects a leak current flowing in a word line WL in performing forming. Patent Literature 3 (PLT 3) discloses that, in performing forming, current supply is performed to supply a constant current to a bit line BL, and at the same time, a compensating current having the same current value as that of the leak current is supplied to the bit line BL based on the leak current detected by the detection circuit.